refactor(viewport): unify content-viewport clipping on the stencil path

Rectangular paper viewports now go through the same GPU stencil clip as
non-rectangular ones: viewport_clip_boundary_ndc returns the four rect
corners (a full-target mask) instead of nothing, so the render path has
no rect/non-rect special case — every content viewport carries a clip
boundary and draws with stencil reference 0xFF.

With a single clip path, the old per-wire / -image / -wipeout scissor
mechanism is fully dead and removed: compute_*_scissors, the
*_pixel_scissors buffers, the project_scissor helper, the per-pass
set_scissor_rect blocks, the vp_scissor field threaded through
WireModel / ImageModel / HatchModel and their GPU mirrors (WireGpu /
ImageGpu / WipeoutGpu / HatchWebGpu), from_run's scissor parameter, the
scissor grouping in build_wire_buffers, and the is_arena_eligible gate.
Net -245 lines across 54 files.

Rectangular viewports still clip exactly via their own render rectangle;
the stencil mask is a redundant full-target no-op there, kept only so
the clip code path stays uniform. XCLIP keeps its CPU wire clip.

Co-Authored-By: Claude Opus 4.8 <[email protected]>

src/modules/draw/draw/attdef.rs

@@ -186,7 +186,6 @@ impl CadCommand for AttdefCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })

src/modules/draw/draw/hatch.rs

@@ -242,7 +242,6 @@ impl HatchCommand {
             scale: 1.0,
             world_origin: origin,
             boundary_wcs: Some(std::sync::Arc::new(wcs)),
-            vp_scissor: None,
             draw_depth: 0.0,
         }
     }
@@ -403,7 +402,6 @@ impl GradientCommand {
             scale: 1.0,
             world_origin: origin,
             boundary_wcs: Some(std::sync::Arc::new(wcs)),
-            vp_scissor: None,
             draw_depth: 0.0,
         }
     }
@@ -577,7 +575,6 @@ impl CadCommand for BoundaryCommand {
                     scale: 1.0,
                     world_origin: origin,
                     boundary_wcs: Some(std::sync::Arc::new(wcs)),
-                    vp_scissor: None,
                     draw_depth: 0.0,
                 };
                 CmdResult::CommitHatch(model)

src/modules/draw/draw/mline.rs

@@ -156,7 +156,6 @@ impl CadCommand for MlineCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })

src/modules/draw/draw/raster_image.rs

@@ -128,7 +128,6 @@ impl CadCommand for ImageCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })

src/modules/draw/draw/ray.rs

@@ -104,7 +104,6 @@ impl CadCommand for RayCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })
@@ -203,7 +202,6 @@ impl CadCommand for XLineCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })

src/modules/draw/draw/revcloud.rs

@@ -109,7 +109,6 @@ impl CadCommand for RevCloudCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })

src/modules/draw/draw/wipeout.rs

@@ -140,7 +140,6 @@ impl CadCommand for WipeoutCommand {
                     key_vertices: vec![],
                     aabb: WireModel::UNBOUNDED_AABB,
                     plinegen: true,
-                    vp_scissor: None,
                     fill_tris: vec![],
                     fill_tris_low: Vec::new(),
                 })
@@ -181,7 +180,6 @@ impl CadCommand for WipeoutCommand {
                     key_vertices: vec![],
                     aabb: WireModel::UNBOUNDED_AABB,
                     plinegen: true,
-                    vp_scissor: None,
                     fill_tris: vec![],
                     fill_tris_low: Vec::new(),
                 })

src/modules/draw/inquiry/area.rs

@@ -89,7 +89,6 @@ impl CadCommand for AreaCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })

src/modules/draw/inquiry/dist.rs

@@ -86,7 +86,6 @@ impl CadCommand for DistCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         })

src/modules/draw/inquiry/measuregeom.rs

@@ -87,7 +87,6 @@ impl MeasureGeomCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
-            vp_scissor: None,
             fill_tris: vec![],
             fill_tris_low: Vec::new(),
         }

src/modules/draw/modify/trim.rs

@@ -3079,7 +3079,6 @@ fn preview_wire(points: Vec<[f32; 3]>, color: [f32; 4], name: &str) -> WireModel
         key_vertices: vec![],
         aabb: WireModel::UNBOUNDED_AABB,
         plinegen: true,
-        vp_scissor: None,
         fill_tris: vec![],
         fill_tris_low: Vec::new(),
     }