feat: GPU scissor rect for paper-space viewport wires

Viewport-projected wires now clip at pixel level to their viewport boundary.

- WireModel.vp_scissor: Option<[f32; 4]> — paper-space bbox set on projection
- WireGpu.vp_scissor carries it through to the draw loop
- Pipeline.compute_wire_scissors() converts paper→NDC→pixel each frame
- render() calls set_scissor_rect() per wire, reset after viewport group
- INTEGRATION_GAPS.md: Viewport ⚠️ → ✅, all 51 gaps resolved

Co-Authored-By: Claude Sonnet 4.6 <[email protected]>

src/modules/home/draw/attdef.rs

@@ -135,6 +135,7 @@ impl CadCommand for AttdefCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/draw/ellipse.rs

@@ -528,5 +528,6 @@ fn line_wire(from: Vec3, to: Vec3) -> WireModel {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
     }
 }

src/modules/home/draw/line.rs

@@ -89,6 +89,7 @@ impl CadCommand for LineCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/draw/mline.rs

@@ -114,6 +114,7 @@ impl CadCommand for MlineCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/draw/raster_image.rs

@@ -113,6 +113,7 @@ impl CadCommand for ImageCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/draw/ray.rs

@@ -87,6 +87,7 @@ impl CadCommand for RayCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }
@@ -166,6 +167,7 @@ impl CadCommand for XLineCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/draw/revcloud.rs

@@ -84,6 +84,7 @@ impl CadCommand for RevCloudCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/draw/wipeout.rs

@@ -120,6 +120,7 @@ impl CadCommand for WipeoutCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
                 })
             }
             WipeoutMode::Polygonal => {
@@ -142,6 +143,7 @@ impl CadCommand for WipeoutCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
                 })
             }
         }

src/modules/home/inquiry/area.rs

@@ -77,6 +77,7 @@ impl CadCommand for AreaCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/inquiry/dist.rs

@@ -72,6 +72,7 @@ impl CadCommand for DistCommand {
             key_vertices: vec![],
             aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
         })
     }
 }

src/modules/home/modify/stretch.rs

@@ -135,6 +135,7 @@ impl CadCommand for StretchCommand {
                     key_vertices: vec![],
                     aabb: WireModel::UNBOUNDED_AABB,
             plinegen: true,
+            vp_scissor: None,
                 })
             }
             _ => None,