fix(solid): skip display-cache wires when ACIS parses; real centres

The embedded solid display-cache wires are body-local (unplaced), and
R2013+ AcDs-backed solids used to misparse them into garbage points near
the origin — a clipped region rendered a stray fragment at (0,0,0). When
the ACIS payload parses, the mesh pipeline (fill + feature edges +
isolines, all body-placed) is the authoritative render, so the wires now
only serve as a last resort for unreadable ACIS data.

acadrust bump brings the decoded wireframe section and real reference
points: solids/regions report the file's stored bounding-box centre (or
a geometry-derived one) instead of (0,0,0), which feeds OCS grips,
Position properties and insertion snaps.

Co-Authored-By: Claude Fable 5 <[email protected]>

src/scene/convert/tessellate.rs

@@ -1706,6 +1706,13 @@ fn solid_wire_fallback(entity: &EntityType) -> Vec<[f64; 3]> {
     if wires.is_empty() {
         return vec![];
     }
+    // Parseable ACIS → the mesh pipeline draws the body (placed); the embedded
+    // display-cache wires are body-local and would render unplaced at the
+    // origin (garbage for AcDs-backed solids). Only unreadable ACIS falls
+    // back to them.
+    if crate::entities::solid3d::acis_parses(entity) {
+        return vec![];
+    }
 
     let mut pts: Vec<[f64; 3]> = Vec::new();
     for wire in wires {